The present invention relates to semiconductor memory devices having error correction code (ECC), and more particularly, to a data output control circuit.
Recently, there has been an increased demand for semiconductor memory devices that are capable of having high integration and high storage capacity. As semiconductor memory devices are increasingly integrated to obtain greater storage capacity, the number of defects among the memory cells concomitantly increases to contribute to a low yield in the productivity of these semiconductor memory devices. In order to address problems of defects and low yield, a semiconductor memory device using an error correction code (hereinafter referred to as an ECC) has recently been proposed to correct errors occurring as a result of defective memory cells. An error correction code is a systematically constructed redundant code capable of correcting an error bit when an error occurs in those bits constituting a block code. In a semiconductor memory device with an error correction code circuit, high integration of the chip must be maintained identically during formation of the chip; and the characteristics of the chip, such as high speed operations, the suppression of current dissipation and the like, must be identical in a semiconductor memory device without the ECC circuit. The high speed operation and current dissipation of the chip are mainly determined by a data output control circuit. Therefore, the construction of the data output control circuit can assert substantial influence on the characteristics of the chip.
When a chip is operated, an operating current generated in the chip is increased during transitions between the input data and the output data, i.e. , during a swing operation of the data to provide a large amount of operating current at output terminals. An increase in the operating current due to undesirable variations at the input/output terminals is detrimental to the effectiveness of the chip. The chip may be liable to malfunction. Moreover, the problem is exacerbated if the chip is highly integrated, especially in case of byte wide memory devices having a plurality of input/output terminals (.times.8, .times.16, etc...). Moreover, the deterioration of access time is inevitably propagated in the chip with the normal state and abnormal state corrected by the ECC circuit, or in memory cells with the normal and abnormal states of a single chip due to undesirable variations at the input/output terminals, thereby resulting in low yield.